NoC Design and Performance Optimization

Systems-on-Chip (SoCs) and Chip Multiprocessors (CMPs) have strong global communication requirements, and networks-on-chip (NoCs) have been proposed as a scalable solution to overcome these communication challenges. This work explores the application of NoCs in both SoCs and CMPs. For SoCs, our work considers the application-specific NoC architecture design problem in a 3D environment. We present an efficient 3D NoC synthesis algorithm, based on simulated allocation (a stochastic method for traffic flow routing), interleaving between floorplanning and NoC synthesis, and accurate power and delay models for NoC components. For CMPs, we observe that intermittent traffic patterns imply that voltage and frequency scaling can be used effectively to reduce NoC energy consumption, but the associated increase in latency and degradation in throughput must be managed. We propose flexible pipeline routers where pipeline stages are reconfigured upon frequency scaling. By reducing the number of pipeline stages, the proposed router enables us to scale down the network frequency without increasing router latency. I. APPLICATION-SPECIFIC 3D NOC DESIGN Three dimensional (3D) integrated circuits, in which multiple tiers are stacked above each other and vertically interconnected using through-silicon vias (TSVs), are emerging as a promising technology for SoCs [1], [2]. In the context of intrachip communication, 3D technologies have created significant opportunities and challenges in the design of low latency, low power and high bandwidth interconnection networks. In 2D SoCs choked by interconnect limitations, networks-onchip (NoCs), composed of switches and links, have been proposed as a scalable solution to the global communication challenges: compared to previous architectures for on-chip communication such as bus-based and point-to-point networks, NoCs have been shown to provide better predictability, lower power consumption and greater scalability [3], [4]. 3D circuits enable the design of more complex and more highly interconnected systems: in this context, NoCs promise major benefits, but impose new constraints and limitations. 3D NoC design introduces new issues, such as the technology constraints on the number of TSVs that can be supported, problems related to optimally determining tier assignments and the placement of switches in 3D circuits, and accurate power and delay modeling issues for 3D interconnects. Our work [5] addresses the problem of designing application-specific 3D NoC architectures for custom SoC designs, in conjunction with floorplanning. Our approach has three significant features that together make it uniquely different from competing approaches: first, we use improved traffic flow routing using a stochastic flow allocation method Simulated Allocation (SAL) that accommodates a realistic objective function with components that are nonlinear and/or unavailable in closed form; second, we interleave floorplanning with NoC synthesis, using specific measures that encourage convergence by discouraging blocks from moving from their locations in each iteration; and third, we use an accurate NoC delay model that incorporates the effects of queueing delays and network contention. A. The Overall Design Flow The design flow of our NoC synthesis algorithm is presented in Fig. 1. Given a given a core graph, we first obtain an initial floorplan of the cores using a thermally-aware floorplanner. This precedes the 3D NoC synthesis step, and is important because the core locations significantly influence the NoC architecture. Associating concrete core positions with the NoC synthesis step better enables it to account for link delays and power dissipation. Application-specific